1. Field of the Invention
The present invention relates to an image sensor and a manufacturing method thereof, and more particularly, to an image sensor capable of greatly improving a physical and electrical bonding force between a photodiode and a substrate including readout circuitry, by adopting a vertical photodiode, and a method of manufacturing the same.
2. Discussion of the Related Art
One type of complementary metal oxide semiconductor (CMOS) image sensor is structured in such a manner that a photodiode that receives light and converts an optical signal to an electric signal is horizontally adjacent to a transistor region that processes the electric signal. Such a horizontal-type image sensor is restricted to increase a light receiving area, that is, a fill factor in a limited area.
In order to overcome the restriction, the photodiode may be vapor-deposited using amorphous silicon (Si). Alternatively, the readout circuitry may be formed on a Si semiconductor while the photodiode is formed in a separate wafer, then bonded to the substrate containing the readout circuitry by wafer-to-wafer bonding. Such a structure will be referred to as a 3D image sensor. The photodiode and the readout circuitry are connected to each other by a metal line.
In case of wafer-to-wafer bonding, however, the bonding force may be insufficient because bonding surfaces of the wafers may be uneven. More specifically, since a metal line connecting the photodiode with a circuit region is exposed at the surface of the interlayer dielectric, the surface profile of the interlayer dielectric may become uneven, thereby deteriorating the bonding force to the photodiode formed on the interlayer dielectric.
A deep via hole may be formed in the wafer including the photodiode to interconnect the photodiode and the readout circuit region. After that, a metal layer connecting the deep via hole with the metal line on the wafer with the readout circuitry may be formed, and then a plug may be formed by selectively etching the metal layer. However, the etching for forming the plug has such a poor uniformity that variations may be induced according to pixels or wafers (e.g., pixel-to-pixel variations and/or wafer-to-wafer variations).